1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a high voltage IC (HVIC) using a silicon substrate on an insulator (SOI) and its manufacturing method.
2. Discussion of the Background
FIG. 25 is an illustration showing a background high voltage IC (HVIC). As shown in FIG. 25, the high voltage IC (HVIC) includes a control section and a power section. The control section includes an oscillation circuit, a control circuit, a logic circuit, a current limit control circuit, a level shift circuit, and an overheat protection circuit, and the power section serves as a high-breakdown-voltage power device. This construction makes it possible to design on one chip both logic LSIs, such as a CMOS and a Bipolar-CMOS constituting the control section, and the high-breakdown-voltage power device constituting the power section.
FIG. 26 is a sectional view showing a high voltage IC (HVIC) using a background SOI substrate. In FIG. 26, the high voltage IC (HVIC) includes a semiconductor substrate 101, an embedded oxide film 102, a SOI layer 103 serving as a device forming region, a silicon oxide film 104, and a device separation region 133. A plurality of CMOSs and Bipolar-CMOSs of the control section are formed on one side separated by the device separation region 133, and a plurality of IGBTs (Insulated Gate Bipolar Transistors) of the power section are formed on the other side separated by the region 133.
An SOI substrate includes the semiconductor substrate 101, embedded oxide film 102, and SOI layer 103. In CMOS and Bipolar-CMOS forming regions, a plurality of wells and source/drains are formed on the SOI layer 103 and one or more gates and electrodes are formed on each well and source/drain region. In an IGBT forming region, a plurality of emitters and collectors are formed on the SOI layer 103 and one or more gates and electrodes are formed on the emitter and collector regions.
By using an SOI substrate, it is possible to decrease parasitic capacitance between devices and between a device and the substrate. Moreover, by combining the SOI substrate with the trench separation technique, it is possible to realize complete dielectric separation. Thereby, the reliability of device operations is improved and a surface separation area can be decreased. Therefore, it is possible to improve the integration level of a chip.
Moreover, by using the SOI substrate, a breakdown voltage can be raised by the RESURF (REduced SURface Field) effect and a design of the breakdown voltage can be done relatively easily by combining SOI substrate parameters such as an SOI thickness (tsoi), SOI specific resistance (rsoi), and embedded oxide film thickness (toxi). It is shown in an article, "S. Merchant,: ISPSD Proc., 1991, pp. 31-35, REALIZATION OF HIGH BREAKDOWN VOLTAGE (&gt;700 V) IN THIN SOI DEVICES", that the combination of thickness of an SOI layer and an embedded oxide film is effective to design a high breakdown voltage.
The RESURF effect is described below by referring to FIG. 27. FIG. 27 is a sectional view showing an SOI diode which includes a semiconductor substrate 101, an embedded oxide film layer 102, and an SOI layer 103. As shown in FIG. 27, a P+ region 106 serving as an anode of the diode and an N+ region 107 serving as a cathode of the diode are formed on the N- SOI layer 103.
By applying a reverse-blocking voltage to the SO diode, a depletion layer extends horizontally up to the broken lines A and B. The extension of the depletion layer is mainly determined by the concentration of the N- SOI layer 103. Moreover, by forming a short circuit between a back grounded electrode (not illustrated) and the P+ region 106, the depletion layer vertically extends to the broken lines A and C. A field intensity is shown by the following expression. EQU Field intensity E=Power supply voltage VCC/Depletion layer width W.
For the same power supply voltage, field intensity depends on a depletion layer width. Therefore, when the depletion layer width increases, field intensity in the horizontal direction can be moderated.
A method of the combination of a thickened SOI layer with a trench separation technique to raise a breakdown voltage is shown in an article, "N. Yasuhara et al.: IEDM Proc., 1991, pp. 141-144, SOI Device Structure Implementing 650 V High Voltage Output Devices on VLSIs". In this article, it is purposed to obtain a breakdown voltage of 600 V or higher by limiting the thickness of an embedded oxide film to 3 .mu.m or less and increasing the thickness of an SOI layer up to approximately 20 .mu.m. When a bonded SOI substrate is used, the thickness of a SOI layer can be relatively easily increased only by adjusting the polishing depth of a portion for the SOI layer.
Further, a method for realizing a high breakdown voltage by increasing the thickness of an embedded oxide film is shown in an article, "ISPSD, Proc., 1994, pp. 183-186, High Voltage Trench Drain LDMOS-FET Using SOI Wafer".
A bonded SOI substrate is used to simplify a manufacturing method to increase the thickness of an SOI layer and an embedded oxide film. In this method, a surface of a semiconductor substrate having a silicon oxide film on its surface is joined with a surface of another semiconductor substrate having or not having a silicon oxide film on its surface, and then either side is polished to obtain an SOI substrate SOI including an SOI layer, an embedded oxide film layer, and a semiconductor substrate.
When a bonded SOI substrate is used to realize a high breakdown voltage by increasing the thickness of an SOI layer, the thick SOI layer can be obtained relatively easily only by adjusting the polishing depth of a portion of the SOI layer. However, problems occur in a separation process that a trench groove must be deepened for separation and that the etching time is increased.
On the other hand, when the thickness of an embedded oxide film is increased to realize a high breakdown voltage, the warp of an SOI substrate becomes a problem. When the thickness of the embedded oxide film is increased by the CVD method to the thickness range of several microns or more, the embedded oxide film does not adhere well with a semiconductor substrate for an SOI layer due to surface roughness of the formed oxide film. Moreover, because of one side formation of an oxide film, a stress is applied between the semiconductor substrate and the embedded oxide film to cause a warp that impairs the bondage with the SOI layer.
When the thickness of an embedded oxide film is increased by thermal oxidation, an oxide film is formed on both sides of a semiconductor substrate, and thereafter, another semiconductor substrate serving as an SOI layer is bonded to either side, and an SOI substrate is formed including the SOI layer, embedded oxide film, semiconductor substrate, and oxide film. In the case of a thermal oxide film, the problem of surface roughness does not occur even in a region of a film thickness of several microns or more. Moreover, because the thermal oxide films are formed on both sides of a semiconductor substrate, stresses applied to both sides of the semiconductor substrate by the silicon oxide films are balanced so that warp does not occur when the silicon oxide films are formed.
However if the thicknesses of the silicon oxide films on the surfaces are decreased due to an oxide film etchant, at the time of SOI layer formation and in the subsequent process, and the balance of stresses applied between the semiconductor substrate and the silicon oxide films is lost between both sides of the semiconductor substrate, a warp of an SOI substrate occurs.
FIG. 28 is a sectional view showing a warp of an SOI substrate shown in "ISPSD, Proc., 1994, pp. 183-186, High Voltage Trench Drain LDMOS-FET Using SOI Wafer". In FIG. 28, the SOI substrate includes a semiconductor substrate 101, an embedded oxide film 102, and an SOI layer 103. As shown in FIG. 28, a warp in the tensile mode is recognized on the SOI substrate.
FIG. 29 is a graph showing the relation between an embedded oxide film layer toxi of an SOI substrate and warp W of the substrate with a parameter of thickness tSOI of the SOI layer 103. In the case of a 5 inch diameter substrate, warp W of the SOI substrate reaches 100 .mu.m when the thickness toxi of the embedded oxide film 102 is 1.7 .mu.m. The graph also shows that the warp W increases proportionally not to the thickness tSOI of the SOI layer, but to the thickness toxi of the embedded oxide film.
A warp of an SOI substrate works as a stress between a semiconductor substrate and an embedded oxide film and decreases the service life of a semiconductor device. And, in the manufacturing process of the semiconductor device, the warpage causes process troubles such as a transfer error, a defective pattern due to deviation of an exposed focal point, and a vacuum attraction error, and greatly affects the yield.